I applied through college or university. I interviewed at Cadence Design Systems
Interview
Resume based shortlisting. Two technical round and one hr round. Online interview through webex. One candidate has 3 technical round and one HR round. No online test conducted since openings are less. each technical round duration is 45 minutes
Given a combinational circuit and asked to find stuck at fault. Last gate is xnor. And he said it is stuck at fault 0 and there is only one stuck at fault
Puzzle. There are 20 coins. 5 heads and 15 trails. You can't see or feel them. And you should make them two groups such that no of heads are equal in both groups
I applied through college or university. The process took 5 days. I interviewed at Cadence Design Systems (Pune) in Jun 2019
Interview
Interview process involved aptitude test which contained questions on counter circuits and other digital circuits, basic aptitude followed by 3 rounds of technical interview and one HR interview. The overall process was very smooth and HR is very cooperative
Interview questions [1]
Question 1
Basics of Digital Electronics, Bit manipulation questions, Verilog questions, questions on pipeline
The process took 6 days. I interviewed at Cadence Design Systems (Pune)
Interview
This is regarding pune location which is tensilica group.
During F2F i didn't feel its Cadence. During first round interviewer was asking previous projects and trying to understand what work have done along with some basic questions and if i stuck some were he was giving hints, second person was bit rude and was not interested at all during interview he was going outside, questions were simple though. like swapping and lot of arithmetic operations even i showed them using SV they want it again same thing in C or othey way which might be related to there work or somthing they want specific approch but his behaviour and way of talking was unprofessional that behaviour bounds to think me again to work in this culture and avoid questions.
Interview questions [1]
Question 1
swaping in sv, c and lot of arithmetic operations and bit of uvm.