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I was asked questions on Verilog/VHDL basics, Testbench concepts, RTL coding, FSM models. system verilog assertions etc. questions related to past work and VLSI flow. Digital design concepts like adders, fsm, logic optimizations.
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Application Engineer I

Interviewed at Synopsys

3.8★
Oct 7, 2022

I was asked questions on Verilog/VHDL basics, Testbench concepts, RTL coding, FSM models. system verilog assertions etc. questions related to past work and VLSI flow. Digital design concepts like adders, fsm, logic optimizations.

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