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Asic Design Engineer Interview Questions
811 asic design engineer interview questions shared by candidates
How to build a synchronizer for one bit, for multiple bits and for clock domains that run at different frequencies? How to do truncate and the sign extension in arithmetic operation (at first I did not catch the point, and the interviewer guide me to the right answer)?
All the questions are very straightforward, like the definitions of setup time and hold time, and how to avoid setup and hold time violation.
What is the difference between the syn and asyn FIFO? Is there any way for cross domain signal transfer? Tell me related technique and writing verilog code to describe it.
mostly regular
Describe the 5 stages in MIPS pipeline structure.
fifo design
The phone screen with basic questions like your visa status.
Low power design, STA
STA, power analysis and optimization, asynchronous fifo, clock domain crossing,seq detector fsm, counter, other verilog problems, synthesis, minor verification qs, comp arch topics like out of order execution, tomasolu, cache,
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