Explain POCV coefficient based calculation for an actual timing report.
Asic Design Engineer Interview Questions
811 asic design engineer interview questions shared by candidates
design uvm driver
Write an SV constraint to generate 4 non-overlapping memory regions of size 32,64,128,256 in 4k memory region.
1) What are slow and fast corners 2) Where we check Setup and Hold 3) FSM questions
Write a C++ function that returns the second largest number in an array
Write a function in C that reverses a linked list
About pd
Why you do clk gating in your design
How to determine which register you want to gate in netlist ?
Static Timing Analysis, Setup time, Hold time, Clock gating, Clock Path Pessimism Removal, Digital design flow, Vmin
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