How to implement gates with mux
Asic Design Engineer Interview Questions
811 asic design engineer interview questions shared by candidates
Digital Systems such as multiplexers, logic gates
What will affect power consumption?
They gave a class - asked to create it's objects and send out random objects in a function.
Intro and things worked on. Then he asked me deep about the project I was working on. Synchronous FIFO question. Wrote for 50 continuous cycle s in any 100 cycles but reading every alternate cycles. Depth reqd? How to design synch fifo ? How async fifo ? Is it possible to write and read from sync FIFO built using single port sram in same clock cycle ? Setup time and why we need it ? How will multiply by 63 ? Optimize way of finding the square of a number ? 1, 4, 9, 16, 25,
all about resume, STA, DFT, Pipelining
Personal research, DVFS, CDC, metastable, asynchronous FIFO, synchronizer, level shifter, clock gating, power gating, dynamic power, leakage power.
Explain Setup and hold for a latch.
transistor sizing for a NAND gate
Design a FIFO hardware
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