How to divide a clock by 3 without using PLL?
Design Digitale Interview Questions
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Typical verilog questions which you find
3) Flip flop A -> Flip flop B -> Flip flop C - output of Flip flop is C is connected to Flip flop A. Combinational delay between A and B is 3ns, b/w B and C is 4ns, b/w C and A is 5ns. Case a) Find max operating freq? [setup = 1ns, hold = 1ns,clock to q =0] Case b) Now make the flip flop B , neg edge triggered . Find max operating freq?
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Explain stability of the amplifier,
What are the channel in AXI and ACE? What is cache coherency?
They asked questions about FPGA , Digital Electronics , Op Amps , Network questions .
Questions on digital design. Implement an equation using 2:1 muxes, implement 3 ip NAND using 2 input NANDs
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