Few puzzles and Projects in my resume
Design Verification Engineer Interview Questions
1,115 design verification engineer interview questions shared by candidates
That's all i can share . Practice your basics. All the best !
Questions mostly about the project. Basics of Pcie protocol
Question about digital design and system verilog and uvm related questions
Computer Architecture, Logic design, validation, software, behavioral.
consider a transaction between two components (data -8 bits and address- 32 bit) .Mismatch happens between expected and received data , What are the expected issues ?
They asked about mu uvm design verification project
functional coverage, types of bins, types of array, constraint examples, virtual class,threads
Digital Logic, Computer Architecture, SystemVerilog, UVM, basic PERl
mux tree, FSM, Regions, NBA, DDR, Swapping of variables, crystal oscillator, full adder using 2x1 mux
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