Pipeline , caches, TLB , virtual memory
Design Verification Engineer Interview Questions
1,115 design verification engineer interview questions shared by candidates
Why is program block needed. What is clocking block. Program for clock without always. Differnce between always_combo and always.
If you have a DC power supply in series with a 1k resistor and a 6k resistor, give the equation that described the voltage across the 6k resistor. Switch the 6k resistor for an inductor, what is the voltage across the inductor? Switch the inductor for a capacitor, what is the voltage across the 1k resistor? Change de the 1k resistor for a cap identical to the other one, what is the voltage drop across each cap? Change one of the caps to make it double the capacity of the other one, what is the voltage drop across each cap?
What did you do in your last job?
completely based on system verilog and digital design concepts
Talk about resume, explain the detail. ask some related questions on the project.
Basics of UVM and SV
Grilled on my current work, System Verilog basics, UVM in depth, Comp Arch questions like Cache coherency.
Should be ready to write some logic (C/Verilog/System Verilog) on the spot
Energy - cost - time trade offs
Viewing 731 - 740 interview questions