difference of Union and Struct (C++). VIPT cache.
Design Verification Engineer Interview Questions
1,114 design verification engineer interview questions shared by candidates
design an electrical circuit with switches, voltage source for a particular application- wasn't expecting one since my area of expertise is mostly digital
2 signals, both only toggle once. At the first rising edge, start testbench; At the second falling edge, stop testbench. How?
Memory Consistency
Design an FSM for a 2-clock system
There are block box modules, and you know nothing about what they are doing, behaior, output, input. Can you create a verification TB for it?
What is gray code and 8b10b encoding, and why they are useful
Q. What are all run-phases and in detail discussion about it Q. Basic constraints related to dist, and assertion
What would you use a modport for?
1. What are the pros and cons of adding an extra stage in a CPU 2. Follow-up: How does adding a stage affect the setup time and hold time
Viewing 911 - 920 interview questions