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Design Verification Interview Questions
1,116 design verification interview questions shared by candidates
Edge trigger variation coding in RTL
1)data should be <20, this was the constraint existed, but you should make the data in range 30 to 40 without using constraint_mode. 2) what the uses of bins in coverage
CDC, HW design, testbench engineering, etc..
Implement a circuit board the receives an 8-bit bus. The output is an 8-bit bus where the first net that is '1' in the input is also '1' in the output, the rest are '0' (in other words - "find first '1' in the input bus).
General questions in Python, C, Verilog, and SystemVerilog.
How to use muxes to implement an XOR gate?
1. About the company, why apple 2. About projects as per resume-interesting test case, negative test case 3. different types of Hazard and how to avoid those 4. pipelining concept 5. Problem-solving: (using associative array-)how to sort names without repetition
Describe fully how a processor works in as much detail as possible.
Leetcode easy questions were asked
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