1. what is the alternate for analyis port 2. related to fork join 3. interrupt handling
Design Verification Interview Questions
1,116 design verification interview questions shared by candidates
Tips for round 2- keep your basics strong. Don't need much. Just got get played by interviewers. If you're stuck or don't know the answer. Atleast try for an approach and keep asking for feedback. Before solving any question, explain your approach and then proceed. Your behaviour shouldn't be like digital systems, either 0 or 1. It should be like analog. Keep explaining every step. And don't say anything that you can't explain. Tips for round 3- Just don't lie. Speak the truth. Don't mention GATE scores in CV. Deny any further studies plan from your side. Just say that you'll do it if your firm wants you to upgrade your skills and be more productive for firm. Else you have no plans. Preferred location - Always say Noida.
They asked me about uvm
apptiude was about the quantative, digital and a simple program. digital question are also simple you can search on internet. programming are also questions.
Debugging scenarios of latest project
About uvm Sv Ethernet Pcie Amba
What is Setup time and Hold Time? Verilog and C syntax related Questions. Questions of Digital Electronics
Call uvm_agent function from uvm_sequence to display "hello world"
1) Write the full adder code and testbench in Verilog? 2) Truth table of JK and D flip flop? 3) Why do glitches occur, and how to solve them? 4) Implement NAND gate using mux?
Questions on FSM, STA, FPGA, Verilog Basics, SV Basics,
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