Question on Static Timing Analysis
Digital Design Engineer Interview Questions
821 digital design engineer interview questions shared by candidates
Design by 3 clock divider using 3 different ways
we discussed about project and some core topics
Asked me to design a state machine to detect two different sequences (overlapping case) using minimum states without going for state reduction.
Extension of design issues in the project undertaken
Draw state diagram for working of a lift for two floors
He asked digital puzzles and risc architevture
Basic setup, hold time. Register based design
R u interested in highers
1) Transistor questions including delay,period and combination logic 2) VHDL/Verilog 3) Clock Divider
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