FIFO setup/hold time state machine
Digital Design Interview Questions
823 digital design interview questions shared by candidates
design cycle and verification plan, polymorphism, inheritance, diff between python and perl, which to use when, blocking vs non blocking assignment, X vs Z in verilog, UVM phases, scoreboard vs monitor, etc
How to use muxes to implement an XOR gate?
Anything from coding to schematics to sta to low power to verification
What are the ways to reduce power consumption?
How to deal with multiple asynchronous clocks in your digital design
Resume based and Verilog based questions Basic digital electronics
Would you do anything differently if you could start you thesis again?
What are some examples of scripts you have wrote, and give some scripting solutions to a problem, e.g. parsing timing reports.
How many quarters would it take to stack end to end from the ground to the top of the empire state building. State your assumptions.
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