phone interview focus on resume!! Very in detail!!! Even ask you how you chose those component, how you implement your algorithm in FPGA, what technique you used and how? any problem you met and how you solved it.
Physical Design Interview Questions
711 physical design interview questions shared by candidates
Technical questions regarding previous project worked and some basic electronics questions
Explain setup and hold timing paths in a static timing report.
Most of them are expected questions like design flow, tools used etc., The most difficult question is, they asked about all the tools used in mentor graphics, cadence and synopsys.
mathematics
Describe your previous work
STA, CTS, Floor planning, Logic Circuits, PNR 1. What is OCV and derate factors 2. Calculation of setup and hold slack (Given values, Thold, Tsetup, Tlogic, derate factors) 3. How to reduce setup violations and hold violations? 4. Difference between H-tree and Mesh? 5. Techniques to reduce clock power? 6. Low power design techniques 7. What is Multi Bit FF? 8. Draw basic logic gates (And) using NOR (NAND) gates? 9. Crosstalk glitches? 10. Placement of macros questions 11. How to calculate channel spacing between macros/ 12. SRAM design questions 13. Physical only cells- Tap cells, Tie cells use and where do we place them 14. How Delay of a net/cell changes with VDD/ 15. Capacitance and Resistance of wire effects on delay and how to reduce it? 16. How to reduce static, Dynamic, short -circuit power? 17. Where to use LVT, HVT cells? 18. Difference between local skew and global skew? 19. Verilog Coding question- Synchronous and Asynchronous DFF 20. What is the use of End cap cells and Decap cells?
How slack effects the frequency in design flow.?
He asked me about my design project which I did during my Masters, Timing analysis, Flipflops, PD Flow
What was the major challenge you faced while working on this project?
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