Senior Software Design Engineer Interview Questions

Mixed Signal Design Engineering

Interviewed at Analog Bits

4.2★

Oct 8, 2014

When connected two NMOSs at their drains, say NMOS1 and NMOS2, assign Vg1=3V, Vg2=4V, Vs1=5V, what will be the voltage at Vs2? What is the working region of NMOS2

Design Engineer

Interviewed at Swiss Ranks

3.8★

Oct 29, 2020

all based on mechanical engineer they provide concept development interview also

Network Design Engineer

Interviewed at Huawei Technologies

3.4★

Jan 27, 2022

What do you know about TCP/IP?

Design Intern

Interviewed at Compass

3.9★

Dec 1, 2016

How do you overcome the situation when you have different opinions with the clients?

Trainee Design Engineer

Interviewed at Harita TVS

3.1★

Nov 23, 2020

Define FMEA in your perspective?

Design Engineering

Interviewed at Ittiam Systems

3.6★

Feb 20, 2010

What is the run time of binary sort?

Product Design Engineer

Interviewed at NIFCO America Corp

3.4★

Jul 27, 2015

Why are man hole covers round?

Training Design Specialist

Interviewed at Alaska USA

3.4★

Jan 10, 2023

Are you willing to relocate to AZ or AK?

ASIC Design Engineer

Interviewed at Broadcom

3.3★

Oct 6, 2011

how to generate a clock divide by 3

Design Verification Engineer

Interviewed at AMD

4★

Aug 16, 2022

An arbiter with an asynchronous reset receives four requests signals, R1, R2, R3, R4 and generates four grant signals, G1, G2, G3, G4. Request R1 has the highest priority and request R4 has the lowest priority. Draw the state diagram.