Not a behavrioal interview, pure coding interview
Senior Verification Engineer Interview Questions
3,657 senior verification engineer interview questions shared by candidates
I was asked on basics of SV,UVM and computer architecture
Tell me about your self
1 Digital Design implementation questions.. ex logic gates design using mux, flipflop vs latch 2. Verilog questions ... always vs initial blocks, blocking vs nonblocking, casex vs casez, timing regions
About the multiplexers in digital electronics
Flipflop and latch difference? Mod5 asynchronous counter circuit
SV and UVM based questions
Explain factory method in UVM
What is config.db in UVM
1. Explain about your self, 2. About your projects, 3. Questions on UVM. 4. Questions on AHB 5. what kind of projects you are working 6. Are you developed any UVC, Scoreboard. 7. Explain about monitor and SB communication. 8. UVM flow 9. Sequencer and driver communication 10. About config_db. all questions are on google based
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