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Senior Verification Engineer Interview Questions
3,655 senior verification engineer interview questions shared by candidates
Design a FSM to detect a certain sequence of numbers.
como voce se ve daqui 19 anos
basic digital design design ,pointers from c language ,basic verilog questions
State machines, VHDL, basic logic and design.
qustions asked in written test are based on the following topics 1.design of FSM 2. STA 3.design of some logic functions and reduction of logic functions face to face in interview are the questions given in the written test.
describe a project you worked on..
all technical questions about the projects on my resume
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Questions like blocking assignment and non blocking assignment difference
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