OOP and polymorphism. Basic System Verilog and UVM coding.
Senior Verification Engineer Interview Questions
3,655 senior verification engineer interview questions shared by candidates
Convert the RTL logic to a gatelvel netlist. Constraint question from system verilog.
3 Question 1 about one of my own projects, Question 2 about verification (Giving a situation which test would you run), Question 3 is a software question write a function that checks if the given input is a palindrome which is simple but then they start to make it harder and harder count how much palindromes there is in 1 string and now the same while getting the input 1 by 1 ... in O(nlogn) or O(n)
How to deal with clock domain crossing issues, timings in logic circuits etc
ou have 100 people standing in a line, each wearing either a black or white hat. Each person can see the hats of the people standing in front of them, but not their own hat or the hats of anyone behind them. Starting from the back of the line, each person is asked to announce the color of their own hat, and they can only say "black" or "white." How can you maximize the number of people who correctly guess the color of their hat?
About a time I stood up to authority. One of my top favorite interview questions of all time.
What is the challenge you face when you start a New job?
The first team I interviewed with asked about: Computer architecture basics: Pipelines, branching and hazards, and hardware-based computer organization themed questions. The questions were along the lines of: 1) Tell me about the performance implications of a deep pipeline. 2) What do "volatile" and "virtual" mean in programming? 3) Define RISC vs. CISC differences. They also asked questions on course work in progress, completed, and projects listed on my resume. The second interview team was more behavioral, asking questions about projects and coding experiences.
How do you verify this logic block?(a black box with some input and outputs and the timing diagram is given
They asked detailed questions about memory and interconnect design in advanced systems. They also gave me a small assignment which I had to do online.
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