1. Constraint coding for specific scenarios. 2. UVm phasing
Soc Analyst Interview Questions
1,153 soc analyst interview questions shared by candidates
Definition of sta and pd design flow
Did u work on proof point. ?
Static Timing Analysis and its tools used
Solving k-maps, coding latch vs flip flop in VHDL/verilog, problems in placement and routing, how to resolve layout issues like drc's
Knowledge of Coding (Not extensive- Basic) Where do you see yourself in next 5-10 years?
Mapas de Karnaugh. Manejo de memorias.
Questions about debug of failure
PD concepts, Timing, STA, Extraction, RTL design
Write a Scoreboard for verifying the average of 5 previous values, where the data is coming sequentially, I.e 1 value at every posedge of clk.
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