Some system verilog Questions
Soc Design Engineer Interview Questions
114 soc design engineer interview questions shared by candidates
Draw an XOR out of NAND gates, logic minimalization, draw FSM for given signals and how many flip flops are needed to implement the design?
Basically covered VLSI basics, ASIC flow basics (each step) and scripting. Friendly chat for behavioral interview.
CMOS inverter questions. Power related questions
Area of the design in my past project. Best design practices. Antenna effects.
Pseudo code for MUX Setup and hold time
What was the major challenge you faced while working on this project?
STA, CTS, Floor planning, Logic Circuits, PNR 1. What is OCV and derate factors 2. Calculation of setup and hold slack (Given values, Thold, Tsetup, Tlogic, derate factors) 3. How to reduce setup violations and hold violations? 4. Difference between H-tree and Mesh? 5. Techniques to reduce clock power? 6. Low power design techniques 7. What is Multi Bit FF? 8. Draw basic logic gates (And) using NOR (NAND) gates? 9. Crosstalk glitches? 10. Placement of macros questions 11. How to calculate channel spacing between macros/ 12. SRAM design questions 13. Physical only cells- Tap cells, Tie cells use and where do we place them 14. How Delay of a net/cell changes with VDD/ 15. Capacitance and Resistance of wire effects on delay and how to reduce it? 16. How to reduce static, Dynamic, short -circuit power? 17. Where to use LVT, HVT cells? 18. Difference between local skew and global skew? 19. Verilog Coding question- Synchronous and Asynchronous DFF 20. What is the use of End cap cells and Decap cells?
1) C++ code to set the matrix MxN to zero if any element in MxN is zero. (leetcode medium question) 2) write constraint to set 32 bit address to be word aligned and 1kb in length
Hold and setup time, FSMs
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