Write code for a UVC mimicing a memory . Reactive sequence in UVM
Verification Design Engineer Interview Questions
1,116 verification design engineer interview questions shared by candidates
FIbonacci series
do I know objective-oriented coding
how to design a FSM using switch-case / shift register
Computer Architecture, Caches, Algorithms, Software Engineering
Do you have prior experience with UVM and System Verilog
1) C++ code to set the matrix MxN to zero if any element in MxN is zero. (leetcode medium question) 2) write constraint to set 32 bit address to be word aligned and 1kb in length
I was given a direct coding question about how I would determine whether two patterns given to me were correct.
Asked lots of questions about Cache and Virtual Memory, including Cache set, index, associativity, etc. CPU superscalar, Out of Order, etc. Address translation, aliasing problem
Verification plan of any given design, assertions, what is coverage?
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