How would you write a test with randomized input (with bounds)?
Verification Design Engineer Interview Questions
1,116 verification design engineer interview questions shared by candidates
Launch 5 (t1,t2,t3,t4,t5) tasks in parallel, wait for 4 of the tasks to be done and kill the task t3.
Design scoreboard to compare dut and reference model.
Write SV assertion for a req/ack protocol
UVM , system verilog and scoreboars related questions.
Design a Flip Flop using transistors.
Design a Cache, 32KB, 40 bit address, 64 Byte cache line, 4 way associative. How many bits are required to implement true LRU?
2nd phone interview: different methods for floating point multiplication.
Asked to explain the different BFM's i worked on and few questions on them.
How do u rate in RTRT and ADA
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