Delayed assignment and delayed evaluation in Verilog
Verification Engineer Interview Questions
3,655 verification engineer interview questions shared by candidates
Digital questions, UVM environment based questions
What is crosstalk? Ways to fix crosstalk? Relationship between Resistance/Capacitance to Length & Width What is charge sharing? How to fix? What is body effect? What is short channel effect? List several effects.
What is an isolation cell?
What do you like to do in your free time?(yeah)
If there is a bowl of fruit and you are one fruit what fruit will you be and why.
Asked about Basic Signalling like Block Section Working, Logic Circuits, Control Table Checking, Signalling Plan, CBTC Principles, Automation in C#, Process Automation & outcome. Success Ratio & feasibility of Automation in Signalling
c++ basics - virtual functions, function vs task difference, coverage , constraints
Verilog code for basic circuits
Can we override constraints like data members?
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