digital electronics ,Verilog,SV and UVM
Verification Engineer Interview Questions
3,655 verification engineer interview questions shared by candidates
Write verilog code to generate a clock with 25% duty cycle , questions on case equality operator , basic gates using mux .
Verilog, Protocols , System Verilog , UVM
How do you handle difficult customers
Why do you want to work at DTCC
How did you handle criticism of previous work?
What operating systems are you familiar with?
Why do you want to leave your current position?
java script for selection sorting
Question asked: SV -> function can take fork_join?y/n ->to find the bit to represent 4069 = 2^(x) or log 2 base (32) ->Malloc() ->write a integer queue : rand int q[$]; -> task and functions UVM: Sequencer- Driver connection phasing name 3 base class related question
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