What challenges do you see in a cross-team effort for a verification project?
Verification Engineer Interview Questions
3,655 verification engineer interview questions shared by candidates
Know everything in c++. Virtual functions/class. Polymorphism. Be ready to write code on the spot
They gave me a design problem and kept on telling me to optimize it
UVM related questions.How to verify some components.How to verify a an old machine .X and Y dimensions of the screen in pixel was given.Was asked to write the test cases for the same.Was asked to a draw a fsm for a for traffic light signal .Questions related to clock skew,randomization and sorting algorithms
Draw the truth table for a NAND gate.
What are your career goals? Where do you see yourself in five years?
Analog Circuits : Since I had some project work in PLLs I was asked where exactly a flipflop or a delay element should be added in the PLL loop, to resolve a glitch or to ensure that the PLL locks. Device Physics : How does mobility of electrons/holes vary with gate voltage in a MOSFET
CMOS/VLSI, timing, logic on transistor level, Verilog question
Write a function in C that receives a string with brackets i.e: "({})[]" and returns true if the brackets are in correct form (like the example above) or false if the brackets aren't well placed like for example : "((]["
How can you verify or verification approch to a particular scenario? Comple black box texting
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