What is the difference between SV function and Verilog function?
Verification Engineer Interview Questions
3,654 verification engineer interview questions shared by candidates
Just asked basic questions on DSP - upsampling and downsampling
They ask you question to get a feel for how you react to different situations and how your respond to their questions.
Name a time you gave great customer service (followed the "SPIRIT" motto)
Can you tell me your years of experience in ____ ?
Print the relevant parts of this data file out in X,X,X format from a given list that has extra/missing bits of information.
Tell me about a class you like?
How do you handle conflict in the workplace?
verify a FIFO using formal verification techniques and methods to resolve complexity
Implement using simple digital components a system that only transmits a stable signal (only if the logical value is stored N times)
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