The first round had questions based on signal processing, basics of system Verilog, and I was given a take-home coding task to write an RTL code to check if there is an increment, decrement by 1 bit and if not, print error; and verify the same using a class-based testbench.
Where do you see yourself in 5 years?
What classes did you like/dislike?
Do you know object-oriented code?
About Verification Techniques
Would I be comfortable on a probationary period, whereas by the end of 90 days I would meet at least 85% of collection goals to.maontain employment
System Design questions, particularly those related to testing systems
resume.
what do u know about virtual pages
Question regarding Logic design, Verilog ,State Machine- pattern detection, Comp Arch- Pipeline, hazards, cache, associativity, Basic Perl were asked.
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