Constraint randomization based question linking to AXI and memory filling
Verification Engineer Interview Questions
3,654 verification engineer interview questions shared by candidates
Confidential. But related to system verilog and uvm.
how to impliment A=7.5B w/o using *, /
How could you shorten the period of training?
Since the interview was for a hardware position, they asked more software related questions than I expected but were all easy
How do you increase processor speed.
Basic Pipeline questions focused mainly on Branch Prediction and BTB
design a vending machine from architecture to rtl..
Loop unrolling quetions
Node insertion in linked list. Fibonacci series function, hardware to generate Fibonacci series, prime number generation hardware , STA concepts, clock domain crossing, use of synchronizes, skew and setup hold time violation.
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