Basic verilog questions, simple logics, and few opps concepts
Verification Engineer Interview Questions
3,654 verification engineer interview questions shared by candidates
UVM Analysis ports and uvm testbench
tell me the UVM testbench execution flow
How would you write a testplan for a FIFO? Create an AND gate from NAND gates. How do you select 2 values from an array whose sum is some value p in linear time?
1 easy and 1 medium level leet code problem along with unit test and expected output of a program.
They asked why I wanted the role, why I wanted to work for the company and questions around the role.
Describe the testbench hierarchy in UVM
MCDC TCs Basic C and python questions Questions from the previous project and skill set
write a code that given a number (int) and the desirable base - will convert the number to the new base and returns an int
Digital Design Concepts of FIFO..??
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