Blocking vs nonblocking Flip-flops vs latch Uvmphases
Verification Engineer Interview Questions
3,652 verification engineer interview questions shared by candidates
Digital: difference between latch n ff, race condition, sequential and Combinational, asynchronous and synchronous Verilog and system verilog: coding problems, assertions, race condition, functions and tasks, union, oop concept etc
What is blocking and non blocking What is logi,c wire , reg differ What is polymorphism What is inhertance What is object and components What is TLM port analysis port
Verilog, STA, FSM. Just go through these topics
Digital electronics, Verilog, System Verilog, UVM
Constraints, p_sequencer, m_sequencer, tb flow, agent
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set up time, hold time
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-Questions about cache coherency -Basic Verilog Questions -Questions about c++ and traversing trees
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