What is setup and hold time What is skew What is synchronous and asynchronous reset
Verification Engineer Interview Questions
3,652 verification engineer interview questions shared by candidates
Design a FSM to detect a certain sequence of numbers.
Build a NAND gate using the given logic gates, A and B. they have truth tables shown here:
1. Programming questions like Fibonacci series. 2. Some questions related to Perl Programming. 3. Some questions on state machine design. 4. Synthesizable and non synthesizable constructs in Verilog. 5. Be thorough with the stuff on the resume.
digital, sv, uvm, verilog, scripting basics
set up time, hold time
-Questions about cache coherency -Basic Verilog Questions -Questions about c++ and traversing trees
I was asked about basic C++ knowledge, such as encapsulation and polymorphism. I was also asked to interpret some assembly code. A design manager asked me conceptual questions about computer systems and architecture, such as cache and virtual memory.
Design an FSM for an elevator, different kinds of coverage, describe some RTL bugs you found in your current role, describe UVM testbench, how are sequences and drivers connected
FIFO depth, and ASYNC FIFO test plan
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