How do you connect UVM objects.
Verification Engineer Interview Questions
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Questions regarding STA mode and Transactor based Simulation Acceleration: How would you implement a transactor? Use SystemC or System Verilog and why? How will you communicate between the DUT and the transactor testbench? Explain the PCIe speedbridge interface and how would you debug it?
Few questions on LDO and Bandgap reference
Single ended CMOS based differential amplifier operation Mark inverting and non inverting terminals Derive expression for gain and output resistance and it's poles and zeros
Q: What is the use of the factory in UVM?
Basic electronics question - 2:1 Mux, truthtable, DFF, FPGA design flow
Virtual Methods , Virtual classes and their difference in system verilog
Questions around GPU pipeline and how it works. Command streamer etc
Draw the IDD diagram (current as a function of time) of an inverter when the input switches from OFF to ON.
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