Was there a time you disagree with the procedure to accomplish a task?
Verification Engineer Interview Questions
3,654 verification engineer interview questions shared by candidates
Having both design and verification work experience, they were keenly interested in whether I wanted to continue in the design arena or stay with verification
What experience do I have ?
Why do you want to work here? Time when you had to problem solve.
what are the qualities of the company and do you know who we service by being a cardinal health at home employee
First round tested around major system verilog ,verilog and UVM concepts
What is your typical working style?
Given variable vector should be randomised as unique values but without using a system verilog keyword which is generally used
Explain different phases in the UVM and their importance?
Topics like pipelining & hazards, Cache, Assembly language, VHDL, C, frequncy divider, clock gneration using VHDL are touched in the technical rounds. And a question to explain my project from digital design is asked.
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