STA, power analysis and optimization, asynchronous fifo, clock domain crossing,seq detector fsm, counter, other verilog problems, synthesis, minor verification qs, comp arch topics like out of order execution, tomasolu, cache,
Asic Engineer Interview Questions
1,319 asic engineer interview questions shared by candidates
I was also asked about why CMOS is used in implementing logic gates. Next, I was about sizing of transistors of a 2 input NAND gate.
The second was about state machine, how to output true for every two consecutive 1s.
use 4 bit multiplier to build 8 bit multiplier
Setup and hold time - definitions; there is a branch with one path being setup critical, and another with a hold violation. Given a buffer, where will you place it if both paths should not have violations?
Trick question on FIFOs.
The interview was more related to what you wrote in written exam.
Difference Between Associative array and Dynamic Arrya
Based on algorithm implementation at hardware level.
Swap via value versus reference coding question. Design question about feeding data from producer to consumer (answer uses buffer)
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