design a full adder with 2-1 mux
Senior Asic Design Engineer Interview Questions
811 senior asic design engineer interview questions shared by candidates
design a combinational circuit which counts the number of 1s in a 7-bit input .
How is processor performance affected when the instruction cache hit latency increases? How do you overcome that?
is there any benefit to use cache if there is read miss for every access?
Complete the C function (body) that uses recursion to determine if the string is a palindrome
there are 1000 wires in which any number of them can be swapped among themselves. How many bit patterns would you send at the input side to get the correct number of wires that are swapped?
How many data bits needed to represent A*B+C, all are 8 bit unsigned
Design a divide by 3 counter. Bonus for 50% duty cycle
Why setup in ICG is tough to solve?
Suppose you have a 4-bit shift register made using D-type flip flops with a positive Clock-to-Q delay and a hold time of 0. Is it possible for this circuit to have hold time violations? Why?
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