How do you combine states in a state machine. Do you actually save anything?
Senior Asic Design Engineer Interview Questions
811 senior asic design engineer interview questions shared by candidates
basic timing questions. I accepted the offer.3 rounds for contract position in VLSI Synthesis/STA all fundamentals are needed timing and synthesis prespective
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how to generate a clock divide by 3
what is the 3 Cs in cache miss?
question on clock gating- for an 8-bit wide register ,what are the different ways in which clock gating can be implemented to reduce overall power
Which gate would you prefer in a design? Nand or Nor? why?
Why would you use a Verilog Pre-processor?
1. sequence detector 2. get second largest number of a unsorted array 3. setup and hold time 4. some testing questions.
5. Explain few low power design techniques
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