Possible solution vectors to meet hold violation
Asic Engineer Interview Questions
1,319 asic engineer interview questions shared by candidates
Clock pulse generator STA concepts
Logic gates (inverter using mux), FSM sequence detector, digital design
how to use UVM events and UVM pool
It was a verilog question like "you are designing 2 modules that work together to send 32-bit wide payloads over a single wire"
Digital design and computer architecture
like bangalore as work location
Basic pipelining, C/C++ and Perl coding, Verilog, FSMs, Caches
Floating Point Calculations
Most questions were pretty much standard. What hit me was the being a PhD student, I was asked questions from Sophomore level courses. This was opposite to my previous interview with IBM, where they really RESPECTED my research and analytically walked me through the interview. The questions were 10101 sequence detector, CMOS inverter with just NMOS, importance of caches etc
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