Bus protocols like SPI, ARM etc
Asic Engineer Interview Questions
1,319 asic engineer interview questions shared by candidates
Can't remember.
Pros and cons of vernier TDC
Explain PD flow? Questions on projects done before
program for ring counter and Johnson counter in verilog
program for pattern detector for FSM
write code for generating clock of 50MHz frequency, with 5% jitter and duty cycle.
Q: How do you construct a 4x1 MUX using 2x1 MUXs
Describe AXI bus protocol and experience with it
In the screening call: quetions about your background and personal projects, then 2/3 questions on digital design basics. Questions about Verilog HDL, logic synthesis, timing constraints, metastability, finite state machines, basics of verifications, testbenches, logic gates at transistor level, application of De Morgan law, small problem on digital circuits (counters, clock dividers, FSMs).
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