They gave me a design problem and kept on telling me to optimize it
Design Verification Engineer Interview Questions
1,115 design verification engineer interview questions shared by candidates
He asked me about Data hazards, Instruction sets , Examples of branch prediction , 32 bit adder design. WAR and RAW Instruction examples. Basic Computer architecture questions.
All the questions were pretty basic and were related to fundamentals of logic design and verification.
Know everything in c++. Virtual functions/class. Polymorphism. Be ready to write code on the spot
Q: How to calculate the depth of FIFO?
Draw the truth table for a NAND gate.
What are your career goals? Where do you see yourself in five years?
CMOS/VLSI, timing, logic on transistor level, Verilog question
Explain how setup time and hold time violations occur and what can be done to reduce there occurence? What is metastability?
Difference between latch and flip flop, Sequence detector design, Divide by n circuits for different values of n. Few scenarios of assertions, Verilog code for positive edge detector and negative edge detector, Setup and Hold time and few codes to debug and provide output. basic questions in digital on mux, questions on code synthesizing
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