UVM, SystemVerilog and PCIe protocol
Design Verification Engineer Interview Questions
1,115 design verification engineer interview questions shared by candidates
Screening - shallow copy, deep copy (explain with code), polymorphism, virtual functions and overriding, sizing the dimensions of a multi dimensional array, constraints unique elements in a 2d array, sv events Panel - Constraints to generate unique address, aligned addresses, task for a driver with some conditions given (follow up -> response packet), using fork join for parallel driver, write driver for a dut which has 3 independent request channels and 2 independent response channels, sv code to find a number is multiple of 8, find output of sv snippet with mixed blocking and non blocking, use of $cast to check class type, declare and initialise a dynamic array, add an element to the same array while keeping previous ones as well, what are hazards in pipelined arch., dynamic branch prediction , data forwarding, randc without using rand, covergroup to cover overflow address, explain advantages of uvm over sv, how does a test start and end in uvm, what happens to the simulation if no objections are raised, how would you detect a hang in a test, write a task for time out
There were no out of the box questions.
Design a state machine that will print '1' when a binary string divisible by 5 is input. E.g. '0101', '1111' all must output 1.
What's the different of rand and randc
Write an SV constraint to generate 4 non-overlapping memory regions of size 32,64,128,256 in 4k memory region.
They gave a class - asked to create it's objects and send out random objects in a function.
What will affect power consumption?
Explain the latest project you undertook.
Simple C++ programming. Verilog coding for sequence detector
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