1. SV constraint 2. UVM 3. Resume review
Design Verification Engineer Interview Questions
1,115 design verification engineer interview questions shared by candidates
Basics of Digital System Design and Analog Electronics.
For the design verification interview, I haven't prepared at all since I didn't know that it was a verification position, all the questions about programing were not answered well.
can you describe what you worked on in your project, biggest roadblock?
Develop a C algorithm to solve arbitration in bus
How instructions are executed in assembly language? How data is transferred between cpu and cache? Why we need cache, why we don't use main memory? Why cache size is kept small?
Calculate address lines required for memory. Puzzle . FIFO verification test cases. Why computer engineering
Basics of computer architecture, verification, data structures, rtl logic Telephonic interview was basics of RTL design
question on packet transfer inside of test bench from generator to driver... (system verilog concepts)
what is blocking and non blocking?
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