There were 4 rounds - 3 technical and 1 HR.
Design Verification Engineer Interview Questions
1,115 design verification engineer interview questions shared by candidates
Qu’est ce qu’il y a dans un processeur?
Find the depth of a binary tree
Constraint and assertion , gate level simulation
mostly in uvm and sv
Verilog based questions - circuit was given and then i had to give an optimized code for it.
What is register renaming? How it works?
Leetcode style coding problems (array and bit manipulation)
Power of 2, asynchronized and synchronized reset
Verify a packet processing DUT where packets coming in have a certain priority.
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