Most questions were based on STA, timing and some based on PERL.
Physical Design Engineer Interview Questions
711 physical design engineer interview questions shared by candidates
Explain the gate level design of a flipflop. Explain why are we using master-slave configuration?
Questions on Level Shifters, clock domain crossing scenarios with logic circuits .
implement XOR using NANDs Setup and Hold Timing constraints
AOCV and POCV in detail
What is floorplanning, partitioning, etc.
projects, setup / hold violation and mitigation, low power design, device physics
OCV related, Cross-talk related, timing analysis
What if the gap between the macros increases in the floor placement..?
Self intro Input file Floorplan Guidelines to macro Physical cells Taps cells Latchup effect Placement Output reports of placement What is setup and hold How to overcome setup violations
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