What should be the size if it is receiving data and also loosing some packets ?
Senior Asic Design Engineer Interview Questions
811 senior asic design engineer interview questions shared by candidates
-Make a AND/OR gate out of muxes -Count the number of 1's in a 7 bit number using only full adders
1.Inverted temperature effect on STA. the question was based on temperature effects on delay below 65nm technology. how STA works under those conditions at different corners. 2. An interesting question about how latency affects jitter. 3. Maximums kew allowed when lock up latches are used. 4. OCV n questions based on it. 5. CRPR. 6. how does a cell get min n max delay? 7. spef file contents, questions about star-rd extractor working. 8. Internship exp based questions.
Design OR gate using MUX
implement 3 input nand using 2:1 muxes
Read a file in unix and count for the particular word in file using single command script.
design state machine to detect 1101 sequence with overlap
they focused a lot on OOP, which is unexpected given the title that I applied.
How to bring a signal from one clock domain to another
how to design the next generation product with 2 times of throughput?
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