If your constraint block includes values like 0, 1, 4, and 300 to 400, how would you handle that in coverage?
Senior Asic Verification Engineer Interview Questions
274 senior asic verification engineer interview questions shared by candidates
Given a diagram, how would you verify a design/check output data. Computer arch basics and design questions
functional, code coverage ,priority encoder explanation, SV
Calculate bandwidth for 16 bit data bus, data rate: 50 MHz and only 25% of time.
1. Some simple random stimulus with specified constraints
I had a phone screen - basic SV and UVM multiple choice questions. Second round - OOPs concepts, some verification concepts (types of coverage, stimulus).
System verilog, UVM scoreboard/monitor coding
Draw a FSM sequence detector
Traversal of a binary tree to find given value
Linked list, Bit manipulation, Pipeline
Viewing 251 - 260 interview questions
See Interview Questions for Similar Jobs
Vlsi Design EngineerSenior Dft EngineerSenior Asic Design EngineerSenior Vlsi Design EngineerDesign Verification EngineerDigital Asic Design EngineerSenior Asic Fpga Design EngineerAsic Verification EngineerCpu Design EngineerRtl Design EngineerIntegrated Circuit Design EngineerSenior Design Verification EngineerVerificatie Design EngineerFpga Design EngineerSenior Asic Fpga OntwerpingenieurDesign VerificationAnalog Design ManagerFpga Engineer