Implement Coverage for given scenario
Senior Design Verification Engineer Interview Questions
1,116 senior design verification engineer interview questions shared by candidates
how to balance the pipeline stage to achieve any specific time period?
A question about managing branching methodology when dealing with IP cores.
Compare Superscalar and VLIW processors.
Why did you not raise alarm on a certain issue? (I didn't think it was that important, but the interviewer thinks it is very important - again a smile that hints that my team is not doing the right thing, according to him).
FSM: Pattern detection 101 in a given sequence --> Change design from Moore to Mealey machine; Lots of questions based on Computer Architecture ( Memory-Cache heirarchy), Test Case scenarios, Signal Tx-Rx rates based question,
f/3 counter design using FSM
they focused a lot on OOP, which is unexpected given the title that I applied.
Do you know anything about RISC Architecture?
1. Write a constraint to generate 4 variables which are unique
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