Basic digital, verilog questionscan be answered if you know the concepts well, Sv was totally into randomization , coverage and assertions. Uvm basic things initial rounds and in depth in last round. In manager round all digital, verilog, sv and uvm were covered
Q: Design d-ff using Mux?
Do you like to document things?
System Verilog and UVM based questions
Are you a team player?
There's a circuit diagram of a pulse generator: a 2-input NAND gate with one of the inputs three inverters downstream from the other input, with some propagation delay for each inverter. Given the timing diagram of the input, what does the output look like?
Project overview, tech stack, Ai/ml
How do you find if the memory is little or big endian
a brief description of yourself and resume
Questions about fork join, queues
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