Designing multiple Gates or some basic logic using Multiplexers. Draw state Diagram & verilog code for 1010 sequence detector.
Senior Design Verification Engineer Interview Questions
1,116 senior design verification engineer interview questions shared by candidates
Questions were from device physics, Analog Design basics like a current mirror, charge pump, LC-VCO, lumped components based circuits, Analog layout, PVT variations effects on basic analog blocks, so on, mostly from my previous work experience.
Setup and hold constraints in a circuit
design a FSM based on a given bus protocol
What is the difference between Moore and melay circuits? Implement and write a code to detect 10110 Sequence? Frequency divide by 7 UVM phrases What is inheritence, ploymorphism, and abstraction in SystemVerilog?
All medium level questions in digital.
digital electronics ,Verilog,SV and UVM
Question asked: SV -> function can take fork_join?y/n ->to find the bit to represent 4069 = 2^(x) or log 2 base (32) ->Malloc() ->write a integer queue : rand int q[$]; -> task and functions UVM: Sequencer- Driver connection phasing name 3 base class related question
write SVA according to given requirement
What's the different of rand and randc
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