They gave me a design problem and kept on telling me to optimize it
Senior Design Verification Engineer Interview Questions
1,116 senior design verification engineer interview questions shared by candidates
Draw the truth table for a NAND gate.
What are your career goals? Where do you see yourself in five years?
CMOS/VLSI, timing, logic on transistor level, Verilog question
Write a function in C that receives a string with brackets i.e: "({})[]" and returns true if the brackets are in correct form (like the example above) or false if the brackets aren't well placed like for example : "((]["
Generate clock using always and forever in verilog
Screening - shallow copy, deep copy (explain with code), polymorphism, virtual functions and overriding, sizing the dimensions of a multi dimensional array, constraints unique elements in a 2d array, sv events Panel - Constraints to generate unique address, aligned addresses, task for a driver with some conditions given (follow up -> response packet), using fork join for parallel driver, write driver for a dut which has 3 independent request channels and 2 independent response channels, sv code to find a number is multiple of 8, find output of sv snippet with mixed blocking and non blocking, use of $cast to check class type, declare and initialise a dynamic array, add an element to the same array while keeping previous ones as well, what are hazards in pipelined arch., dynamic branch prediction , data forwarding, randc without using rand, covergroup to cover overflow address, explain advantages of uvm over sv, how does a test start and end in uvm, what happens to the simulation if no objections are raised, how would you detect a hang in a test, write a task for time out
Digital design basics, SV, UVM, SVA
Tell me about yourself and then questions on verilog
How to maximize clock frequency in digital circuit.
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