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Senior Design Verification Engineer Interview Questions
1,116 senior design verification engineer interview questions shared by candidates
Can you talk about your past experiences?
General questions about C, pipelining, caching, hazards and more C.
Functional coverage vs. Code Coverage
What is an Agent? Passive vs. Active.
what is Synchronous reset and asynchronous reset?
Abstarct class vs Interface, inheritance,polymorphism…..etc Observer and Factory DP in details. Log file output analysis. Behavioural questions. Giving basic and simple designs with some specifications and elaborate a strategy to verify it.
what is function overriding and overloading
Draw the circuit base on the coding provided
Difference between Verilog and SV. Difference between blocking and non-blocking. Inheritance and virtual functions. Many C codes such as reverse an array, reverse bits of a number, get all even bits of a number, Fibonacci series, generate a random floating point number between a and b, Find a number in an array for which sum of all elements to its left= sum of all elements to its right. Few questions on digital logic such as finding minimum gates required for a given truth table, sequence detector, generate AND gate from 2 input mux etc.
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